Some integrated circuits include a charge pump to generate a supply voltage "on-chip". Moreover, in some circuits the charge pump is used to generate a boosted voltage. As used herein, a boosted voltage is a voltage that is greater than the greatest "off-chip" supply voltage (e.g., the VCC supply voltage). For example, a boosted supply voltage can be used to turn on a N-channel field effect transistor (NFET) pull-up device in an output circuit. The boosted gate voltage allows the NFET to pull up the output voltage to essentially the full VCC supply voltage level when the output circuit is to generate a logic high output signal (instead of VCC-Vt as when the gate voltage is not boosted).
In this type of application, the boosted voltage is generally regulated to a value of about VCC+Vtn+Vm, where VCC is the value of the VCC supply voltage, Vtn is the value of the threshold voltage of the NFET and Vm is the value of additional noise margin. A voltage sensing circuit is typically used to monitor the boosted voltage and disable the charge pump when the boosted voltage reaches the value VCC+Vtn+Vm.
The charge pump may include a disable circuit that is configured to receive a control signal from the voltage sensing circuit to enable and disable the charge pump. FIG. 1 is a schematic diagram illustrative of such a disable circuit adapted for use in a memory chip. Disable circuit 10 includes AND gates 11 and 12, OR gate 13, NAND gate 14 and inverter 15. AND gate 11 is a two-input AND gate having its input leads connected to receive an oscillator (osc) signal and an oscillator select (oscsel) signal. The output lead of AND gate 11 is connected to an input lead of two-input OR gate 13. AND gate 12 is also a two-input AND gate, having its input leads connected to receive a row address strobe (ras) signal and a ras select (rassel) signal. The output lead of AND gate 12 is connected to the other input lead of OR gate 13.
NAND gate 14 is a two-input NAND gate having one input lead connected to receive a pump disable (PD) signal via input lead 17 and having the other input lead connected to the output lead 18 of OR gate 13. Typically, a voltage sensing circuit (not shown) monitors the boosted voltage and generates signal PD, which is configured to indicate whether the boosted voltage exceeds a predetermined maximum value. The output lead of NAND gate 14 is connected to an input lead of inverter 15. The output lead of inverter 15 is connected to an input lead 19 of a two-phase charge pump circuit (CPC) 16. Inverter 15 outputs a pump control (PC) signal that causes CPC 16 to "fire" or perform a pump cycle with every transition of signal PC to pump charge to increase the boosted voltage.
One of the problems with disable circuit 10 is that when signal PD is asserted to disable CPC 16, disable circuit 10 may generate an extra transition in signal PC, thereby causing the boosted voltage to exceed the predetermined maximum value. FIG. 2 is a timing diagram illustrating such an occurrence during the operation of disable circuit 10. Referring to FIGS. 1 and 2, the output signal generated by OR gate 13 is represented by a waveform 21. In this example, signal oscsel is at a logic high level, whereas signal rassel is at a logic low level. Consequently, AND gate 11 outputs to OR gate 13 a signal essentially equivalent to signal osc, while AND gate 12 outputs a logic low level to OR gate 13. As a result, OR gate 13 outputs a pre-pump control (PPC) signal that is substantially equivalent to signal osc from the ring oscillator (not shown).
As described above, signal PD is generated by the aforementioned voltage sensing circuit and is represented in FIG. 2 by a waveform 22. In this example, signal PD is an active low signal. Thus, when the boosted voltage exceeds the predetermined maximum value, signal PD transitions to a logic low level to initiate de-activation of CPC 16. Signal PC, generated by inverter 15, is represented by a waveform 23. When signal PD is de-asserted (i.e., logic high), NAND gate 14 functions essentially like an inverter to generate a signal equivalent to a complemented version of signal osc. Inverter 15 then complements the output signal from NAND gate 14 to generate signal PC as a slightly delayed version of signal osc. More particularly, a rising edge 24.sub.1 in waveform 21 causes a rising edge 24.sub.2 in waveform 23. Similarly, a falling edge 25.sub.1 in waveform 21 causes a falling edge 25.sub.2 in waveform 23.
However, when signal PD is asserted so that falling edge 26 in waveform 22 occurs while signal PCC is at a logic high level (indicated by portion 27 of waveform 21), the output signal generated by NAND gate 14 will transition from a logic low level to a logic high level signal. As a result, the falling edge of signal PD causes a high-to-low transition of signal PC as indicated by falling edge 28 of waveform 23. Thus, an extra transition undesirably occurs in signal PC after signal PD is asserted, thereby allowing CPC 16 to increase the boosted voltage beyond the predetermined maximum value. Accordingly, there is a need for a disable circuit for a two-phase charge pump that does not allow a transition of signal PC after signal PD is asserted.